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Many 8-bit processors, such as Motorola's 6800 and MOS Technology's 6502 make use of a single pin to indicate to the rest of the system whether the CPU wishes to read from or write to a memory location (e.g. logic high = read, logic low = write). Other contemporary processors, including National Semiconductor's SC/MP and Zilog'z Z80 used two pins, one each for read and write operations.

This difference lead to some interesting design combinations, such as Acorn's System 1 computer, which used a 6502 CPU and National Semiconductor INS8154 I/O chip (originally designed for the SC/MP). The 6502's R/W pin was inverted and gated by the CPU clock to generate the separate NRDS and NWDS signals required by the INS8154.

I can appreciate why it would be desirable to combine the read and write signals onto a single pin, especially as you wouldn't have more than 40 pins per chip. I don't see any clear advantages of keeping them on separate pins instead, though.

What reasons would CPU designers have for choosing these different approaches?

What reasons would CPU designers have for choosing these different approaches?

It depends on what creates a valid cycle, so what is the 'leading' signal for it. In a more general way it's the design view of the bus.

Common ways (*1) are:

• The 8080 way - Marking a cycle by a one of several dedicated signal marking the type of cycle as well as it's validity. RD and WR mark a read or write cycle as well as the validity of all other signals (*2).




• The 6800 way - A dedicated signal marks the validity of an access cycle, putting all other in context. VMA (Valid Memory Address) is output to indicate a cycle. R/W defines the direction of this cycle.




• The 6500 way - Each and every clock cycle is a valid access cycle. No dedicated signal is needed, the clock signal can be used for this purpose. R/W defines the direction.

So while there is a basic difference in the way a bus is viewed between the 8080 and 6800 way, both need two signals to create a valid cycle and direction. The 8080 solution is more simple to decode in peripherals, especially if build up from general TTL, while the 6800 got a more abstract view. Both have the advantage that I/O and memory does not need to be clocked. And both do as well offer simple ways for DMA/bus-sharing.

The 6500 way is a simplification of the 6800 bis design (*3). By making each and every clock cycle a bus cycle (and having the CPU output a valid direction and address during that), one pin on the CPU could be saved. On the downside non-6500 peripherals had to incooperate the clock signal into their enable decoding (*4). Even more cumbersome the fact that this simplification made DMA/bus-sharing real hard, requiring external buffers and logic (*5).

Then again, the later isn't as much of an issue as it also hits the other schemes as well, depending on the peripheral used.

It may be worth to note that there where many more variations that these three - as there where many more microprocessors.

(For everyones sanity I skip the bus state controlled cycles of an Intels 8008 :))

• From a historic point of view the 6800 way is the most versatile and found in similar was in many mini computers as well as other CPUs - like TI's 9900 (here called MEMory ENable).




• The Signetics/Valvo/Philips 2650 was somewhat similar, but featured in addition to a valid address line (ADRess ENable) a WRitePulse line, only triggered during write cycles - which where as well anounced by a R/W being high. So to some point a mixture of 6800 and 8080 - satisfying both protocols for most parts. The CPU featured as well a quite fine tuned framework for bus sharing.




• Nationals SC/MP takes this a step further by using a multi master bus protocol by default. Only when the bus is granted a bus cycle is indicated by NENOUT, followed by an address strobe (NADS) and then followed by a write or read strobe (NWDS/NRDS). Using - and taking the many internal cycles without bus access into account, two SC/MP coudl be coupled in a system with almost no performance penalty.



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  Speaking of weird, the RCA/Intersil CDP1802 does feature a bus design somewhat like the 8080, with seperate read and write lines (MRD/MWR), but these do not validate otehr signals, but indicate direction ... and to some extend 'alert' components ahead of time - 5 cycles for read and two for write. The transfer itself is initiated by the TPB signal validating the lower address half - which at that point is already valid for more than 3 cycles.

  
  
  

  In fact, it isn't really weird, but far fas away from the simplified and abstract bus designs we are used to see today.

  
  

Bottom line, there was way more than just two ways to access memory (and even more for I/O).

*1 - Processor names are used for simplicity of explanation and will not mark any invention or origin claim.

*2 - IO/M does not - it's just another address line.

*3 - The 6500 development history becomes quite clear when looking at a minimum 6800 system, here Motorola suggests to combine PHI2 and VMA to create a generic Enable signal. With the 6500 design as a simplified, cost reduced 6800 focused on embedded application, having this combination already by default and saving a signal to be outputed was a clear plus - not at least by freeing up pins to make the integrated clock generator work and save even more.

*4 - On the plus side complex 6500 I/O units will have a clock signal already present, which comes handy for any kind of timer/counter application.

*5 - Something various later spin offs eased - all the way of the WDC65C02 reintroducing a 6800 compatible interface.